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M2F1G64CB88A4N / M2F2G64CB8HA4N

1GB: 128M x 64 / 2GB: 256M x 64

Unbuffered DDR3 SDRAM DIMM Preliminary

REV 0.1 1

06/2008

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

240pin Unbuffered DDR3 SDRAM MODULE

Based on 128Mx8 DDR3 SDRAM A Die

Features

• Performance:

• JEDEC Standard 240-pin Dual In-Line Memory Module

• 128Mx64 and 256Mx64 DDR3 Unbuffered DIMM based on

64Mx8 DDR3 Elixir SDRAM

• Intended for 533MHz, 667MHz and 800MHz applications

• Inputs and outputs are SSTL15 compatible

• V

= V

DDQ

= 1.5Volt ± 0.075Volt

• SDRAMs have 8 internal banks for concurrent operation

• Differential clock inputs

• Data is read or written on both clock edges

• 8 bit pre-fetch

• Two different termination values (Rtt_Nom & Rtt_WR)

• Extended operating temperature rage

• Auto Self-Refresh option

• Automatic and controlled precharge commands

• Programmable Operation:

- DIMM  Latency: 5,6,7,8,9,10

- Burst Type: Sequential & Interleave

- Burst Length: BC4, BL8

- Operation: Burst Read and Write

• 14/10/1 Addressing (row/column/rank) – 1GB

• 14/10/2 Addressing (row/column/rank) – 2GB

• Serial Presence Detect

• Gold contacts

• SDRAMs in 78 FBGA Package

• RoHS and Halogen-Free compliance

Description

M2F1G64CB88A4N and M2F2G64CB8HA4N are 240-Pin Double Data Rate 3 (DDR3) Synchronous DRAM Unbuffered Dual In-Line

Memory Module (UDIMM), organized as one-rank 128Mx64 and two ranks 256Mx64 high-speed memory array. M2F1G64CB88A4N

uses eight 128Mx8 DDR3 SDRAMs. M2F2G64CB8HA4N uses sixteen 128Mx8 DDR3 SDRAMs. These DIMMs are manufactured using

raw cards developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation

between suppliers. All Elixir DDR3 SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25” long space-saving

footprint.

The DIMM is intended for use in applications operating up to 533 MHz ( 667MHz or 800MHz) clock speeds and achieves high-speed data

transfer rates of up to 1066Mbps (1333 Mbps or 1600 Mbps). Prior to any access operation, the device  latency and burst / length /

operation type must be programmed into the DIMM by address inputs A0-A13 and I/O inputs BA0, BA1, and BA2 are using for the mode

The DIMM uses serial presence-detect implemented via a serial 2,048-bit EEPROM using a standard IIC protocol. The first 128 bytes of

serial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.

Speed Sort

PC3-8500

PC3-10660

PC3-12800

Unit

-BE

-CG

-DG

DIMM  Latency

Clock Frequency

533

667

800

MHz

Clock Cycle

1.875

1.5

1.25

DQ Burst Frequency

1066

1333

1600

Mbps

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